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APA2058
2.4W Stereo Fully Differential Audio Power Amplifier With Stereo Class AB Cap-free Headphone Driver and LDO
Features
* *
General Description
TM
Meeting VISTA
Requirement
Fully Differential Power Amplifier with Excellent RF Rectification Immunity
The APA2058 is a stereo fully differential audio power amplifier with stereo Class-AB cap-free headphone driver and LDO available in a TQFN5X5-32A pins package. The built-in gain setting at power amplifier can minimize the external component counts. For the flexible application, the gain can be set to 4-steps, 10, 12, 15.6, and 21.6dB by gain control pins (GAIN0 and GAIN1). The power amplifier' s fully differential architecture provides high PSRR, increased immunity to noise and RF rectification. The APA2058 power amplifiers are capable of driving 2.4W at VDD=5V into 4 speaker, the cap-free headphone drivers can provide 180mW at HV DD =3.3V into16 headphones, and the LDO has a maximum 200mA(3.3V) driver current for audio codec. The APA2058 provides thermal and over-current protections. The cap-free headphone driver eliminates the DC blocking capacitors at outputs, save the PCB space. The integration of fully differential power amplifier, cap-free headphone driver, and LDO is a best solution for VISTATM requirement and it can lower the total BOM costs.
* * * * * * * * * * *
No Output Capacitor Required for Head Phone Driver Integrated LDO (Low Dropout Regulator) for Audio Codec (3.3V) Adjustable Gain Setting for Power Amplifier AV=-1.5V/V Fixed Gain Setting for Headphone Driver Fast Start-up Time Integrated De-Pop Circuitry High PSRR (Power Supply Rejection Ratio) Thermal and Over-Current Protections Less External Components Required Space Saving Package - TQFN5x5-32A Lead Free and Green Devices Available (RoHS Compliant)
+0
Common Mode Rejection Ratio (dB)
Applications
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20
* * *
LCD Monitor Notebook Protable DVD
VDD=5.0V RL=4 AV=10dB Vin=0.2VPP Ci=0.47F Input Short AMP Mode
Simplified Application Circuit
Audio Codec
Stereo Speakers
100
1k
10k 20k
Frequency (Hz)
Stereo Headphone LDO (Low Drop -Out Regulator)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 1 www.anpec.com.tw
APA2058
Ordering and Marking Information (Note 1)
APA2058 Assembly Material Handling Code Temperature Range Package Code APA2058 QB :
APA2058 XXXXX
Package Code QB : TQFN5x5-32A Operating Ambient Temperature Range I : -40 to 85 C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device XXXXX - Date Code
Note 1 : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight).
Pin Configuration
23 AMP_EN 20 ROUTP 19 ROUTN 22 HP_EN 21 PGND 18 PVDD 17 HVDD 16 HP_LO 15 HP_RO 14 HVSS TQFN5x5-32A (Top View) 13 CVSS 12 CPN 11 CGND 10 CPP 9 NC RINN_A 1 RINP_A 2 LINP_A 3 LINN_A 4 LOUTP 6 LOUTN 7 PGND 5 PVDD 8 24 BIAS LDO_EN 25 RIN_H 26 LIN_H 27 GND 28 LDOUT 29 VDD 30 GAIN0 31 GAIN1 32
=Thermal-Pad (connected the Thermal-Pad to GND plane for better heat dissipation)
Absolute Maximum Ratings
Symbol VDD HVDD VSS
(Note 2)
Rating -0.3 to 6 -0.3 to 6 -6 to +0.3 -0.3 to VDD+0.3 VSS-0.3 to HVDD+0.3 -0.3 to VDD+0.3 -0.3 to +0.3 V Unit
Parameter Supply Voltage (VDD to GND, PVDD to PGND) Supply Voltage (HVDD to GND) Supply Voltage (HVSS to GND) Input Voltage (RINN_A, RINP_A, LINN_A, LINP_A to GND) Input Voltage (RIN_H, LIN_H to GND) Input Voltage (GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN to GND) Input Voltage (PGND, CGND to GND)
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APA2058
Absolute Maximum Ratings (Cont.)
Symbol TJ TSTG TSDR PD Maximum Junction Temperature Storage Temperature Range Maximum Lead Soldering Temperature, 10 Seconds Power Dissipation Parameter
(Note 2)
Rating 150 -65 to +150 260 Internally Limited W
Unit
C
Notes 2: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol JA JC Parameter Thermal Resistance -Junction to Ambient Thermal Resistance -Junction to Case TQFN5X5-32A (Note 3)
(Note 4)
Typical Value 40 8
Unit
C /W
TQFN5X5-32A Note 3: Please refer to " Layout Recommendation", the Thermal-Pad on the bottom of the IC should soldered directly to the PCB' s Thermal-Pad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz copper thickness. Note 4: The case temperature is measured at the center of the Thermal-Pad on the underside of the TQFN5X5-32A package.
Recommended Operating Conditions
Symbol VDD HVDD VIH VIL Supply Voltage Supply Voltage High Level Input Voltage Low Level Input Voltage GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN For Power Amplifier VIC ILDOUT TA TJ COUT RL RL Common Mode Input Voltage For Headphone Amplifier Output Current (LDOUT) Ambient Temperature Range Junction Temperature Range LDO Output Capacitor (MLCC type) Speaker Resistance Headphone Resistance HVSS ~ HVDD 0 ~ 200 -40 ~ 85 -40 ~ 125 1 ~ 100 4~ 16 ~ F mA
Parameter
Range 4.5 ~ 5.5 3.0 ~ 3.6 2 ~ VDD
Unit
V 0 ~ 0.5 0.5 ~ VDD-0.5
C
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APA2058
Electrical Characteristics
Refer to the typical application circuits. VDD=5V, HVDD=3.3V, Gnd=0V, TA=25 C (unless otherwise noted)
Symbol IDD(HVDD) IDD(VDD) IAMP(HVDD) IAMP(VDD) IHP(HVDD) IHP(VDD) ILDO(HVDD) ILDO(VDD) ISD(HVDD) ISD(VDD) II Input Current Shutdown Current VHP_EN=VLDO_EN=0V LDO Supply Current V AMP_EN =VHP_EN=5V, Headphone Driver Supply Current VLDO_EN=0V V AMP_EN =VLDO_EN=5V, VHP_EN=0V V AMP EN =5V, Power Amplifier Supply Current Parameter Test Conditions Min. V AMP_EN =0V , Supply Current VHP_EN=VLDO_EN=5V V AMP_EN =VHP_EN=VLDO_EN=0V HVDD VDD HVDD VDD HVDD VDD HVDD VDD HVDD VDD APA2058 Typ. 2.5 9 0.1 4.5 2.5 6 0.1 0.4 Max. 4 15 0.2 7.5 4 10 0.2 0.65 2 5 1 A mA Unit
o
GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN CB=0.47F AV=10dB
SPEAKER MODE, AV =10dB TSTART-UP Start-Up Time from Shutdown 17 9.5 11.5 15.1 21.1 25 76 60 40 20 10 12 15.6 21.6 5 1.9 1.3 2.4 1.5 0.07 0.05 -110 -110 -75 -65 100 100 22 10.5 12.5 16.1 22.1 20 W mV dB ms k
Ri
Input Resistor
AV=12dB AV=15.6dB AV=21.6dB VGAIN0=VGAIN1=0V.
AV
Closed-Loop Gain
VGAIN0=0V, VGAIN1=VDD. VGAIN0=VDD, VGAIN1=0V. VGAIN0=VGAIN1=VDD.
VOS
Output Offset Voltage
PO
Output Power
THD+N Crosstal k PSRR CMRR S/N Vn
Total Harmonic Distortion Pulse Noise Channel Separation Power Supply Rejection Ratio Common Mode Rejection Ratio Signal-to-Noise Ratio Noise Output Voltage
RL = 8 THD+N=1%, fin=1kHz RL=4 RL=8 THD+N=10%, fin= kHz RL=4 RL=8 fin=1kHz RL=4 ,PO=1.4W RL=8, PO=0.9W fin=1kHz RL=4, Po=200mW RL=8, Po=130mW fin=217Hz, Vrr=0.2Vrms,RL=8 fin=1kHz, Vin=0.2Vrms.,RL=8 fin=20~20kHz With A-weighting Filter RL=4, PO=1.4W, RL=8, PO=0.9W, fin=20~20kHz,With A-weighting Filter RL=8
1 -
-
-
%
-
Vrms
dB
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APA2058
Electrical Characteristics (Cont.)
Refer to the typical application circuits. VDD=5V, HVDD=3.3V, Gnd=0V, TA=25 C (unless otherwise noted)
Symbol Parameter Test Conditions Min. HEADPHONE MODE, AV = -1.5V/V, CPF=CPO=1F(X5R type) TSTART-UP Ri AV VOS Start-Up Time from shutdown Input Resistor Closed-Loop Gain Output Offset Voltage RL = 32 THD+N=1%, fin=1kHz RL=16 RL=32 THD+N=10%, fin=1kHz RL=16 RL=32 THD+N=1%, fin=1kHz RL=320, RL=10k, THD+N=10%, fin=1kHz RL=320, RL=10k, fin=1kHz RL=16 , PO=125mW RL=32, PO=88mW RL=320, VO=1.5V RL=10k, VO=1.6V fin=1kHz RL=16 , PO=16mW RL=32, PO=12mW RL=320, VO=0.22V RL=10k, VO=0.22V fin=217Hz,Vrr=0.2Vrms RL=32, fin=20~20kHz, With A-weighting Filter RL=16 , PO=125mW RL=32, PO=88mW RL=320, VO=1.5V RL= 10k, VO=1.6V fin=20~20kHz, With A-weighting Filter RL=32 CB=0.47F 17 -1.45 10 20 -1.5 1 140 120 180 160 2.0 2.1 2.45 2.6 0. 03 0. 02 0. 005 0. 004 -82 -82 -77 -77 -80 99 100 100 100 15 -1.55 5 mW ms k V/V mV APA2058 Typ. Max. Unit
o
PO
Output Power
100
150 1.8
V -
VO
Output Swing Voltage
-
THD+N
Total Harmonic Distortion Pulse Noise
-
-
%
Crosstalk
Channel Separation
-
dB -
PSRR
Power Supply Rejection Ratio
-
S/N
Signal-to-Noise Ratio
-
-
Vn
Noise Output Voltage
-
-
Vrms
LDO (LOW DROP-OUT REGULATOR) IO VO Output Current Output Voltage Line Regulation Load Regulation PSRR RDIS Power Supply Rejection Ratio Discharge Resistor IO=1mA IO=1mA, VDD=4.5V to 5.5V IO=1mA to 200mA IO=1mA,fin=120Hz,Vrr=0.2Vrms 3.2 3.3 1.5 0.03 -50 170 200 3.4 5 0.1 mA V mV mV/mA dB
CHARGE PUMP, CPF=CPO=1F(X5R type) FOSC REQ CVss RDIS Oscillator Frequency Equivalent Resistance Negative Output Voltage Discharge Resistor
5
No load -5.1 -
450 10 -5 5
-4.9 -
kHz V k
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APA2058
Block Diagram
LOUTP LINN_A
LINP_A LOUTN GAIN1 GAIN0
Gain Control
PVDD PGND ROUTN
RINP_A
RINN_A ROUTP
LIN_H
HP_LO + HVDD HVSS + HP_RO
GND
RIN_H
VDD PVDD
AMP_EN HP_EN LDO_EN Control LDO Charge Pump
CPP
CPN
BIAS
VDD
LDOUT
CVSS
CGND
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APA2058
Pin Description
PIN NO. 1 2 3 4 5,21 6 7 8,18 9 10 11 12 13 14 15 16 17 19 20 22 23 24 25 26 27 28 29 30 31 32 NAME RINN_A RINP_A LINP_A LINN_A PGND LOUTP LOUTN PVDD NC CPP CGND CPN CVSS HVSS HP_RO HP_LO HVDD ROUTN ROUTP HP_EN AMP_EN BIAS LDO_EN RIN_H LIN_H GND LDOUT VDD GAIN0 GAIN1 I/O/P I I I I P O O P I/O P I/O O P O O P O O I I P I I I P O P I I FUNCTION The inverting input pin of right channel power amplifier. The non-inverting input pin of right channel power amplifier. The non-inverting input pin of left channel power amplifier. The inverting input pin of left channel power amplifier. Power amplifier' ground s The positive output pin of left channel power amplifier. The negative output pin of left channel power amplifier. Power amplifier' supply voltage pin. s No Connection. Charge pump flying capacitor positive connection. Charge pump' ground. s Charge pump flying capacitor negative connection. Charge pump output pin, connect this pin to the "HVSS". Headphone driver' negative supply voltage pin. s The output pin of right channel headphone driver. The output pin of left channel headphone driver. Headphone driver' positive supply voltage pin. s The negative output pin of right channel power amplifier. The positive output pin of right channel power amplifier. Headphone drivers enable input pin; High=Enable. Power amplifiers enable input pin; Low=Enable. Bias voltage for power amplifiers. LDO (Low Drop-Out Regulator) enables input pin; High=Enable. The input pin of right channel headphone driver. The input pin of left channel headphone driver. Control block' ground, connect this pin to CGND and PGND. s LDO (Low Drop-Out Regulator)' output pin. s Control block and LDO supply voltage pin. Control pin for internal gain setting, MSB, Bit 1. Control pin for internal gain setting, LSB, Bit 0.
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APA2058
Typical Application Circuit
Differential input mode
VDD CS3 Gain Control (Amplifier) 1F
29 LDOUT 0.1F 2.2F 32 GAIN1
31 GAIN0
CO2 CO1 Gnd
Regulator Output Ci5 1F
26 RIN_H
25 LDO_EN
Ci6 1F
27 LIN_H
30 VDD
28 GND
Headphone Driver Input Signals Regulator Enable
Right Channel Input Signal (Amplifier) Left Channel Input Signal (Amplifier)
Ci1 RINN_A 0.47F Ci2 RINP_A 0.47F Ci3 LINP_A 0.47F Ci4 LINN_A 0.47F Gnd
1 2 3 4
24 BIAS
CB Gnd Power Amplifier Enable Headphone Driver Enable Gnd
0.47F
23 AMP_EN 22 HP_EN
PGND 5 LOUTP 6 LOUTN 7
APA2058
21 PGND 20 ROUTP 19 ROUTN 18 PVDD 17 HVDD
VDD HVDD CS5 0.1F Gnd
VDD
PVDD 8
CS4
CGND 11 CVSS 13 HVSS 14 HP_RO 15 CPN 12 CPP 10 HP_LO 16
CS2
CS1 0.1F 10F
NC 9
2.2F
CPF
1F
CPO 1F
VSS
Gnd Tip Sleeve
Ring
Single-ended input mode
VDD CS3 Gain Control (Amplifier) 1F
29 LDOUT 0.1F 2.2F
31 GAIN0
Headphone Jack
CO2 CO1 Gnd
Regulator Output Ci5 1F
26 RIN_H
25 LDO_EN
Ci6 1F
32 GAIN1
28 GND
27 LIN_H
30 VDD
Headphone Driver Input Signals Regulator Enable
Ci1 Right Channel GndC Input Signal i2 (Amplifier) Ci3 Left Channel Ci4 Input Signal (Amplifier) Gnd Gnd
RINN_A 1
24 BIAS
CB Gnd Power Amplifier Enable Headphone Driver Enable Gnd
0.47F
RINP_A 2
0.47F
23 AMP_EN 22 HP_EN
0.47F
LINP_A 3
0.47F
LINN_A 4
0.47F
PGND 5 LOUTP 6 LOUTN 7
APA2058
21 PGND 20 ROUTP 19 ROUTN 18 PVDD 17 HVDD
VDD HVDD CS5 0.1F Gnd
VDD
PVDD 8
CS4
CPP 10 CGND 11 CPN 12 CVSS 13 HVSS 14 HP_RO 15 HP_LO 16
CS2
CS1 0.1F 10F
NC 9
2.2F
CPF
1F
CPO 1F
VSS
Gnd Tip Sleeve
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Headphone Jack Ring
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APA2058
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
THD+N vs. Output Power
10
THD+N vs. Frequency
1
THD+N (%)
THD+N (%)
1
RL=4 fin=1kHz Ci=0.47F AV=10dB BW<22kHz AMP Mode
PO=0.14W
0.1
PO=0.7W
PO=1.4W
0.01
VDD=4.5V
0.1
VDD=5.0V VDD=5.5V
VDD=5.0V RL=4 Ci=0.47F AV=10dB BW<22kHz AMP Mode
100 1k 10k 20k
0.01 10m
100m
1
5
0.001 20
Output Power (W)
Frequency (Hz)
Crosstalk vs. Frequency
Common Mode Rejection Ratio (dB)
+0 TT V TTTTT =5.0V
CMRR vs. Frequency
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 100 1k 10k 20k
Crosstalk (dB)
RL=4 AV=10dB Ci=0.47F -40 PO=200mW AMP Mode
-20 -60
DD
VDD=5.0V RL=4 AV=10dB Vin=0.2VPP Ci=0.47F Input Short AMP Mode
-80
Right to Left
-100
Left to Right
-120
-140 20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
THD+N vs. Output Power
10
THD+N vs. Frequency
1
THD+N (%)
1
RL=8 fin=1kHz Ci=0.1F AV=10dB BW<22kHz AMP Mode
PO=0.09W
0.1
VDD=4.5V
0.1
THD+N (%)
PO=0.45W
VDD=5.0V
0.01
VDD=5.5V
0.01 10m 100m 1 5
0.001 20
VDD=5.0V RL=8 AV=10dB Ci=0.47F BW<22kHz AMP Mode
100 1k
PO=0.9W
10k 20k
Output Power (W)
Frequency (Hz)
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APA2058
Typical Operating Characteristics (Cont.)
(TA = +25C, unless otherwise noted.)
Crosstalk vs. Frequency
RL=8 -20 AV=10dB Ci=0.47F -40 PO=130mW AMP Mode
-60 -80
CMRR vs. Frequency
Common Mode Rejection Ratio (dB)
VDD=5.0V RL=8 AV=10dB -20 Vin=0.2VPP -30 Ci=0.47F Input Short -40 AMP Mode
-10 -50 -60 -70 -80 -90 -100 20 100 1k 10k 20k +0
+0 TTTTTT=5.0V VT
DD
Crosstalk (dB)
Right to Left
-100 -120 -140 20
Left to Right
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
Frequency Response
+11 +220
Frequency Response
+22 +220
+10
Gain
+200
+21
Gain
+200
Phase (deg)
+9
+180
+20
+180
Phase VDD=5.0V RL=8 AV=10dB Ci=0.47F AMP Mode
10 100 1k 10k
Phase VDD=5.0V RL=8 AV=21.6dB Ci=0.47F AMP Mode
10 100 1k 10k
+8
+160
+19
+160
+7
+140 200k
+18
+140 200k
Frequency (Hz)
Frequency (Hz)
50u
Output Noise Voltage vs. Frequency
+0
Crosstalk vs. Frequency
-20 -40
Right channel
Output Noise Voltage (Vrms)
Left channel
10u
Crosstalk (dB)
-60 -80
VDD=5.0V HVDD=3.3V RL=4(AMP) RL=10k(HP) PO=200mW(AMP) AMP(active) mode HP mode
VDD=5.0V RL=8 AV=10dB Cin=0.47F A-Wighting AMP Mode
1u 20 100 1k 10k 20k
Left(AMP) to Right(HP)
-100 Right(AMP) to Right(HP)
-120
Left(AMP) to Left(HP)
Right(AMP) to Left(HP)
-140 20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
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Phase (deg)
Gain (dB)
Gain (dB)
APA2058
Typical Operating Characteristics (Cont.)
(TA = +25C, unless otherwise noted.)
THD+N vs. Output Voltage
10
THD+N vs. Output Power
10
1
THD+N (%)
0.1
RL=16 RL=32
THD+N (%)
VDD=5.0V HVDD=3.3V fin=1kHz Ci=1F BW<22kHz In Phase HP Mode
1
VDD=5.0V HVDD=3.3V RL=16 fin=1kHz Ci=1F BW<22kHz HP Mode
In Phase
0.1
Mono
0.01
RL=320 RL=10K
0.001 0 500m 1 1.5 2 2.5 3
0.01 10m
100m
500m
Output Voltage (Vrms)
Output Power (W)
THD+N vs. Frequency
1
Crosstalk vs. Frequency
+0
Crosstalk (dB)
THD+N (%)
0.1
VDD=5.0V HVDD=3.3V RL=16 Ci=1F BW<22kHz HP Mode
-20
PO=13mW
-40 -60
VDD=5.0V HVDD=3.3V RL=16 PO=16mW Ci=1F HP Mode Right to Left
PO=63mW PO=125mW
-80
0.01
Left to Right
-100 -120 -140
0.001
20
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
THD+N vs. Output Power
10
THD+N vs. Frequency
1
THD+N (%)
THD+N (%)
1
VDD=5.0V HVDD=3.3V RL=32 fin=1kHz Ci=1F BW<22kHz HP Mode
0.1
VDD=5.0V HVDD=3.3V RL=32 Ci=1F BW<22kHz HP Mode
PO=9mW
In Phase
0.1
Mono
PO=88mW
0.01
PO=44mW
0.01 10m
100m
300m
0.001
20
100
1k
10k 20k
Output Power (mW)
Frequency (Hz)
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APA2058
Typical Operating Characteristics (Cont.)
(TA = +25C, unless otherwise noted.)
Crosstalk vs. Frequency
+0 -20 -40
50u
Output Noise Voltage vs. Frequency
Output Noise Voltage (Vrms)
Crosstalk (dB)
VDD=5.0V HVDD=3.3V RL=32 PO=12mW Ci=1F HP Mode Right to Left
Left channel
10u
-60 -80
Right channel
Left to Right
-100 -120 -140 20
VDD=5.0V HDD=3.3V RL=32 Ci=1F A-Weighting HP Mode
1u 20 100 1k 10k 20k
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
Frequency Response
+4
Crosstalk vs. Frequency
+220
+0
Gain
T VT =5.0V DD
-20
+3 +200
-40
Crosstalk (dB)
Phase (deg)
-60 -80 -100 -120 -140
HVDD=3.3V RL=8(AMP) RL=16(HP) PO=16mW(HP) AMP Mode HP(active) Mode Left(HP) to Right(AMP) Right(HP) to Left(AMP) Right(HP) to Right(AMP) Left(HP) to Left(AMP)
Gain (dB)
+2
+180
Phase VDD=5.0V HVDD=3.3V RL=32 Ci=1F HP Mode
10 100 1k 10k 200k
+1
+160
+0
+140
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
THD+N vs. Frequency
1
Crosstalk vs. Frequency
+0 -20 -40
Crosstalk (dB)
0.1
THD+N (%)
VDD=5.0V HVDD=3.3V RL=320 Ci=1F BW<22kHz HP Mode
VDD=5.0V HVDD=3.3V RL=320 VO=0.22Vrms Ci=1F HP Mode
Right to Left
-60 -80
Left to Right
VO=0.15V
0.01
-100 -120
VO=0.75V
VO=1.5V
0.001 20 100 1k 10k 20k
-140 20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
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APA2058
Typical Operating Characteristics (Cont.)
(TA = +25C, unless otherwise noted.)
THD+N vs. Frequency
1
Crosstalk vs. Frequency
+0 -20 -40
Crosstalk (dB)
0.1
THD+N (%)
VDD=5.0V HVDD=3.3V RL=10k Ci=1F BW<22kHz HP Mode
VDD=5.0V HVDD=3.3V RL=10k VO=0.22Vrms Ci=1F HP Mode Right to Left
-60 -80
0.01
VO=0.16V VO=1.6V VO=0.8V
100 1k 10k 20k
Left to Right
-100 -120 -140 20
0.001 20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
Output Noise Voltage vs. Frequency
50u
Frequency Response
+4 +220
Output Noise Voltage (Vrms)
Gain
Left channel
10u
+3
+200
Gain (dB)
Right channel
+2
+180
Phase VDD=5.0V HVDD=3.3V RL=10k Ci=0.47F HP Mode
10 100 1k 10k
VDD=5.0V HDD=3.3V RL=10k Ci=1F A-Weighting HP Mode
1u 20 100 1k 10k 20k
+1
+160
+0
+140 200k
Frequency (Hz)
Frequency (Hz)
AMP Attenuation vs. Frequency
+0
HP Attenuation vs. Frequency
-10 -20 -30
-10 -20 -30
AMP Attenuation (dB)
-40 -50 -60 -70 -80 -90 -100 -110 -120 20
HP Attenuation (dB)
VDD=5.0V RL=8 AV=10dB Ci=0.47F VO=2Vrms (AMP enable) AMP Mode (disable)
-40 -50 -60 -70 -80 -90 -100 -110
VDD=5.0V HVDD=3.3V RL=32 Ci=1F VO=1Vrms (HP enable) HP Mode (disable)
Left channel Right channel
Right channel Left channel
100 1k 10k 20k
100
1k
10k 20k
-120 20
Frequency (Hz)
Frequency (Hz)
Copyright (c) ANPEC Electronics Corp. Rev. A.3 - Aug., 2008
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Phase (deg)
APA2058
Typical Operating Characteristics (Cont.)
(TA = +25C, unless otherwise noted.)
HP Attenuation vs. Frequency
+0
-20 T T T
PSRR vs. Frequency
Power Supply Rejection Ratio (dB)
-30 -40 -50 -60 -70 -80 -90
-10 -20
AMP Attenuation (dB)
-30 -40 -50 -60 -70 -80 -90 -100 -110 -120 20
VDD=5.0V HVDD=3.3V RL=10k Ci=1F VO=1Vrms (HP enable) HP Mode (disable)
VDD=5.0V RL=8 AV=10dB Ci=0.47F Vrr=0.2Vrms AMP Mode
Right channel Left channel
-100 -110
Vrr:Ripple Voltage on VDD
20 100 1k 10k 20k
100
1k
10k 20k
-120
Frequency (Hz)
Frequency (Hz)
PSRR vs. Frequency
-20 TTT T TT T
PSRR vs. Frequency
-20 T T TT TT T
Power Supply Rejection Ratio (dB)
Power Supply Rejection Ratio (dB)
-30 -40 -50 -60 -70 -80 -90 -100 -110
VDD=5.0V HVDD=3.3V RL=32 Ci=1F Vrr=0.2Vrms HP Mode
T
-30 -40 -50 -60 -70 -80 -90 -100 -110
VDD=5.0V HVDD=3.3V RL=10k Ci=1F Vrr=0.2Vrms HP Mode
Vrr:Ripple Voltage on HVDD
-120 20 100 1k 10k 20k
Vrr:Ripple Voltage on HVDD
-120 20 100 1k 10k 20k
Frequency (Hz)
Frequency (Hz)
PSRR vs. Frequency
+0
LDO Output Voltage vs. Supply Voltage
3.35 3.34 3.33
Power Supply Rejection Ratio (dB)
Output Voltage (Volt)
VDD=5.0V -10 I =10mA O Vrr=0.2Vrms -20 LDO Mode
-30 -40 -50 -60 -70
LDO Mode
3.32 3.31 3.30 3.29 3.28 3.27 3.26 3.25 4.5 4.7 4.9 5.1 5.3 5.5
IO=10mA
IO=100mA
IO=200mA
Vrr:Ripple Voltage on VDD
-80 20 100 1k 10k 20k
Frequency (Hz)
Supply Voltage (Volt)
Copyright (c) ANPEC Electronics Corp. Rev. A.3 - Aug., 2008
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APA2058
Typical Operating Characteristics (Cont.)
(TA = +25C, unless otherwise noted.)
LDO Drop-Out Voltage vs. Output Current
LDO Mode 0.12
0.15
2.0 1.8 1.6
Power Dissipation vs. Output Power
Drop-Out Voltage (Volt)
Power Dissipation (W)
1.4 1.2 1.0 0.8 0.6 0.4 0.2 VDD=4.5V
VDD=5.5V VDD=5.0V
0.09
0.06
0.03
RL=4 fin=1kHz Mono AMP Mode 0.5 1.0 1.5 2.0 2.5 3.0
0
0
0.1
0.2
0.3
0.0 0.0
Output Current (A)
Output Power (W)
Power Dissipation vs. Output Power
1.0 0.9 0.8
300
Power Dissipation vs. Output Power
250
Power Dissipation (mW)
Power Dissipation (W)
0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.5 1.0 VDD=4.5V RL=8 fin=1kHz Mono AMP Mode 1.5 2.0 VDD=5.5V VDD=5.0V
RL=16
200
150 RL=32 VDD=5.0V HVDD=3.3V fin=1kHz Mono HP Mode 25 50 75 100 125 150 175 200
100
50
0
0
Output Power (W)
Output Power (mW)
Output Power vs. Supply Voltage
3.0 2.8 2.6 RL=4 AV=10dB fin=1kHz Mono AMP Mode THD+N=10%
2.0 1.8
Output Power vs. Supply Voltage
RL=8 AV=10dB fin=1kHz Mono AMP Mode THD+N=10% 1.4
Output Power (W)
Output Power (W)
2.4 2.2 2.0 1.8 1.6 THD+N=1%
1.6
1.2 THD+N=1% 1.0
1.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
0.8 4.5 4.6 4.7
Supply Voltage (V)
Supply Voltage (V)
4.8 4.9 5.0 5.1 5.2
5.3 5.4 5.5
Copyright (c) ANPEC Electronics Corp. Rev. A.3 - Aug., 2008
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APA2058
Typical Operating Characteristics (Cont.)
(TA = +25C, unless otherwise noted.)
Supply Cuttent vs. Output Power
0.8 0.7 VDD=5.5V VDD=5.0V
0.50 0.45 0.40
Supply Cuttent vs. Output Power
VDD=5.5V VDD=5.0V VDD=4.5V
Supply Current (A)
Supply Current (A)
0.6 0.5 0.4 0.3 0.2 0.1 0.0 0.0 0.5
VDD=4.5V
0.35 0.30 0.25 0.20 0.15 0.10 0.05
RL=4 AV=10dB fin=1kHz Mono AMP Mode 1.0 1.5 2.0 2.5 3.0
RL=8 AV=10dB fin=1kHz Mono AMP Mode 0.5
0.00 0.0
Output Power (W)
Output Power (W)
1.0
1.5
2.0
Output Power vs. Load Resistance
2.6 2.4 2.2 VDD=5.0V AV=10dB fin=1kHz Mono AMP Mode
Output Power vs. Load Resistance
250 VDD=5.0V HVDD=3.3V fin=1kHz Mono HP Mode
200
Output Power (W)
1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 4 8 12 16 20 THD+N=1% THD+N=10%
Output Power (W)
2.0
150 THD+N=10% 100 THD+N=1% 50
24
28
32
0 10
100
1000
Load Resistance ()
Load Resistance ()
Supply Current vs. Supply Voltage
11 10
Supply Current vs. Supply Voltage
3.0 VDD=5.0V No Load
HVDD=3.3V No Load
2.5
Supply Current (mA)
9 8 7 6 5 4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 AMP enable IHVDD=0.1mA HP enable IHVDD=2.2mA AMP,HP enable IHVDD=2.2mA
Supply Current (mA)
2.0 1.5 1.0 AMP enable IVDD=4.9mA 3.4 3.4 3.5 3.5 3.6 3.6 AMP,HP enable IVDD=9.3mA HP enable IVDD=5.0mA
0.5 0.0 3.3
Supply Voltage(V)
Supply Voltage(V)
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APA2058
Operating Waveforms
Power On
VDD
Power Off
VDD
1 2 VROUT 3 VHP_RO
1 2 VROUT
3 VHP_RO
CH1: VDD, 2V/Div, DC CH2: VROUT, 20mV/Div, DC CH3: VHP_RO, 20mV/Div, DC TIME: 5ms/Div
CH1: VDD, 2V/Div, DC CH2: VROUT, 20mV/Div, DC CH3: VHP_RO, 20mV/Div, DC TIME: 20ms/Div
Speaker Enable
Speaker Disable
VAMP_EN
1
VAMP_EN
1
VOUTP
VOUTP 2
2
CH1: VAMP_EN, 2V/Div, DC CH2: VOUTP, 1V/Div, AC TIME: 5ms/Div
CH1: VAMP_EN, 2V/Div, DC CH2: VOUTP, 1V/Div, AC TIME: 1ms/Div
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APA2058
Operating Waveforms (Cont.)
Headphone Enable
Headphone Disable
VHP_EN
VHP_EN 1
1
VHP_RO
VHP_RO
2
2
CH1: VHP_EN, 2V/Div, DC CH2: VHP_LO, 1V/Div, AC TIME: 5ms/Div
CH1: VHP_EN, 2V/Div, DC CH2: VHP_LO, 1V/Div, AC TIME: 1ms/Div
LDO Power On
LDO Power Off
VDD 1
VDD
1
VLDOUT
VLDOUT
2
2
CH1: VDD, 2V/Div, DC CH2: VLDOUT, 2V/Div, DC TIME: 200s/Div
CH1: VDD, 2V/Div, DC CH2: VLDOUT, 2V/Div, DC TIME: 20ms/Div
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APA2058
Operating Waveforms (Cont.)
LDO Enable
LDO Disable
VLDO_EN 1
VLDO_EN
1
VLDOUT
VLDOUT
2
2
CH1: VLDO_EN, 2V/Div, DC CH2: VLDOUT, 1V/Div, DC TIME: 1ms/Div
CH1: VLDO_EN, 2V/Div, DC CH2: VLDOUT, 1V/Div, DC TIME: 1ms/Div
LDO Line Transient
1 VDD
LDO Load Transient
ILDOUT 1
2
VLDOUT
VLDOUT 2
CH1: VDD, 1V/Div, DC VDD Offset = 5.5V CH2: VLDOUT, 10mV/Div, DC VLDOUT Offset = 3.3V TIME: 200s/Div
CH1: ILDOUT, 200mA/Div, DC CH2: VLDOUT, 5mV/Div, DC VLDOUT Offset = 3.3V TIME: 200s/Div
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APA2058
Operating Waveforms (Cont.)
GSM Power Supply Rejection vs. Time
GSM Power Supply Rejection vs. Frequency
+0
VDD 1
-50
VROUT 2
AMP Output Voltage (dBV)
-100
+0 -50 -100 -150
-150
3
VHP_RO
CH1: V DD, 500mV/Div, DC VDD Offset = 5.0V CH2: V ROUT , 20mV / Div, DC CH3: VHP_RO , 20mV / Div, DC TIME: 2ms/Div
0
400
800
1.2k
1.6k
2k
Frequency (Hz)
GSM Power Supply Rejection vs. Frequency
-50 -100
HP Output Voltage (dBV)
+0 -50 -100 -150
-150
0
400
800
1.2k
1.6k
2k
Frequency (Hz)
Copyright (c) ANPEC Electronics Corp. Rev. A.3 - Aug., 2008
Supply Voltage (dBV)
+0
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Supply Voltage (dBV)
APA2058
Function Description
Fully Differential Amplifier The APA2058' power amplifier is a fully differential s amplifier with differential inputs and outputs. The fully differential amplifier has some advantages versus traditional amplifier. Firstly, don' need the input coupling cat pacitors because the common-mode feedback will compensate the input bias. The inputs can be biased from 0.5V~VDD-0.5V, and the outputs are still biased at midsupply voltage of the power amplifier. If the inputs are biased out of the input range, the coupling capacitors are required. Secondly, the fully differential amplifier has outstanding immunity against supply voltage ripple (217Hz) caused by GSM RF transmitters' signal, which is better than the typical audio amplifier. Gain Setting Function For the convenient uses, the APA2058' power amplifiers s provide four gain setting options by GAIN0 and GAIN1 pins. GAIN0 0 0 1 1 GAIN1 0 1 0 1 AV(dB) 10 12 15.6 21.6 The Cap-free headphone drivers use a charge pump to invert the positive power supply (VDD) to negative power supply (VSS) (see Figure 1). The headphone amplifiers operate at this bipolar power supply, and the outputs reference refers to the ground. This feature eliminates the output capacitor that using in conventional single-ended headphone amplifiers. In addition, the power supply rail for Cap-free headphone drivers has almost 1.5X compare to the single power supply rail headphone drivers. Thermal Protection The thermal protection circuit limits the junction temperature of the APA2058. When the junction temperature exceeds TJ = +150oC, a thermal sensor turns off the amplifier, allowing the devices to cool. The thermal sensor allows the amplifier to start-up after the junction temperature down about 125 oC. The thermal protection is designed with a 25 o C hysteresis to lower the average TJ during continuous thermal overload conditions, increasing lifetime of the ICs. Over-Current Protection (OCP)
* The power amplifier monitors the output buffers'current.
When the over current occurs, the output buffers'current will be reduced and limited to a fold-back current level. The power amplifier will go back to normal operation until the over-current current situation has been removed. In
HVDD
Headphone Mode Operation
VOUT
addition, if the over-current period is long enough and the IC' junction temperature reaches the thermal protection s threshold, the IC enters thermal protection mode.
HVDD/2 Gnd
Conventional Headphone Driver
* The LDO regulator provides a current-limit circuitry, which monitors and controls P-channel MOS' gate s
limit for extended period time. When the output voltage drops below 0.6V, which is caused by the over load or
HVDD
voltage, limiting the output current to 0.4A. For reliable operation, the device should not be operated in current-
VOUT
Gnd
short circuit, the internal short circuit current-limit circuitry limits the output current down to 250mA. The short circuit current-limit is used to reduce the power dissipation during short circuit condition. The short circuit current-limit has a blanking time feature after the under-voltage lockout threshold is reached, therefore, it will avoid the output causing short circuit current-limit protection during startup; the blanking time is about 600s.
Cap-free Headphone Driver
VSS
Figure 1: The Cap-Free Headphone Driver' Operation s
Copyright (c) ANPEC Electronics Corp. Rev. A.3 - Aug., 2008
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APA2058
Function Description (Cont.)
* The charge pump monitors the output voltage (V
Over-Current Protection (OCP) (Cont.)
SS
). In
addition, it has an over voltage protection to avoid over current occuring on headphone driver' output. When the s output voltage (VSS) is greater than -2V, the charge pump will turn off the charge pump' output. The charge pump' s s output will turn on again if the situation has been removed. Typical under voltage protection threshold is -2V with 0.5V hysteresis. Low Drop-Out (LDO) Regulator The LDO regulator' output provides maximum 200mA s drive capacity for external audio codec. A 2.2F decoupling capacitor with 0.1f capacitor (filtering the high frequency noise) is recommended at LDO regulator ` output. The s LDO regulator has built-in under-voltage lockout circuits to keep the output shuting off until internal circuitry is operating properly. The under-voltage lockout function initiates a soft-start process after input voltage exceeds its rising under-voltage lockout threshold during power on. The internal soft-start circuit controls the rise rate of the output voltage and limits the current surge during startup. Approximate 20s delay time after the VDD is over the under-voltage lockout threshold; the LDO regulator' outs put voltage starts the soft-start. The typical soft-start interval is about 130s and the under-voltage lockout threshold is 2.5V with 0.15V hysteresis. Enable Mode The APA2058 provides the independent enable control functions and allows user disable any main circuit blocks when not in using, and these can save the power consumption. In addition, if either the power amplifier or the headphone driver is disabled, the released time will happen immediately when enable the power amplifier or the headphone driver. However, if both the power amplifier and the headphone driver are disabled at the same time, the released time will be the TSTART-UP Time when enable one of them. Disable all blocks ( V AMP_EN =5V, VHP_EN= VLDO_EN=0V), The APA2058 enters the shutdown mode, and only consumption 5A(Max.) at VDD supply current and 2A(Max.) at HVDD supply current.
Copyright (c) ANPEC Electronics Corp. Rev. A.3 - Aug., 2008
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APA2058
Application Information
Windows VistaTM Premium Mobile Requirement
Device Type Requirement Full Scale Output voltage THD+N Analog Line Output Jack (RL=10k) Line output cross-talk Noise level during system activity Full Scale Output voltage Analog Headphone Output Jack (RL=320) THD+N Headphone output cross-talk Noise level during system activity Full Scale Output voltage Analog Headphone Output Jack (RL=32) THD+N Headphone output cross-talk Noise level during system activity Value 0.707Vrms -65dBFS 20Hz~20kHz -50dB, 20Hz~15kHz -80dBFS A-weighting 0.707Vrms -65dBFS 100Hz~20kHz -50 dB 100Hz~15kHz -80dBFS A-weighting 0.3Vrms -45dBFS 100Hz~20kHz -50dB 100Hz~15kHz -80dBFS A-weighting APA2058 typical performance 2.3Vrms -70dB 20Hz~20kHz -70dB 20Hz~20kHz -100dBFS A-weighting 2.3Vrms -78dB 100Hz~20kHz -75 dB 100Hz~15kHz -100dBFS A-weighting 2.0Vrms -68dB 100Hz~20kHz -70 dB 100Hz~15kHz -100dBFS A-weighting
Input Capacitor (Ci) In the typical application, an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri form a high-pass filter with the corner frequency is determined in the following equation: fC(highpass ) = 1 2 R iC i (1)
leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitors should face the amplifiers' inputs in most applications because the DC level of the amplifiers' inputs are held at VDD/2. Please note that it is important to confirm the capacitor polarity in the application. Power Supply Decoupling Capacitor, Cs The APA2058 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) to be as low as possible. Power supply decoupling also prevents the oscillations caused by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different types of capacitors that target on different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series- resistance (ESR) ceramic capacitor, (0.1F typically) placed as close as possible to the device VDD lead works best. For filtering lower frequency noise signals, a large aluminum electrolytic capacitor of 10F or greater placed near the audio power amplifier is recommended.
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The value of Ci must be considered carefully because it directly affects the low frequency performance of the circuit. Consider the example where Ri is 20k and the specification calls for a flat bass response down to 40Hz. The equation is reconfigured below : 1 Ci = 2 R i fc (2)
Consider the variation of input resistance (Ri), the value of Ci should be 0.2F. Therefore, it' better to choose a s value in the range from 0.22F to 1.0F. A further consideration for this capacitor is the leakage path from the input source through the input network (Ri + Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a lowCopyright (c) ANPEC Electronics Corp. Rev. A.3 - Aug., 2008
APA2058
Application Information (Cont.)
Charge Pump Flying Capacitor (CPF) The flying capacitor affects the load transient of the charge pump. If the capacitor' value is too small, it will degrade s the charge pump' current driver capability and the pers formance of headphone amplifier. Increasing the flying capacitor' value will improve the load transient of charge s pump. Recommend using the low ESR ceramic capacitors (X5R type is recommended) above 1f. Charge Pump Output Capacitor (CPO) The output capacitor' value affects the power ripple dis rectly at VSS. Increasing the value of output capacitor will reduce the power ripple. The ESR of output capacitor affects the load transient of VSS. Low ESR and greater than 1f ceramic capacitor (X5R type is recommended) is recommendation. Layout Recommendation
ThermalVia diameter 0.3mm X 9
1.15mm 0.25mm
2. The output traces should be short, wide ( >50mil), and symmetric. 3. The input trace should be short and symmetric. 4. The power trace width should greater than 50 mil. 5. The TQFN5x5-32A thermal pad should be soldered on PCB, and the ground plane needs solded mask (to avoid short circuit) except the thermal pad area.
0.5mm 3.6mm 4.1mm 3.6mm
Solder Mask to Prevent Short Circuit
TQFN5X5-32A Land Pattern Recommendation
Ground plane for ThermalP AD
Figure 5. TQFN5X5-32A Land Pattern Recommendation 1. All components should be placed close to the APA2058. For example, the input capacitor (Ci) should be close to APA2058' input pins to avoid causing noise cous pling to APA2058' high impedance inputs; the s decoupling capacitor (CS ) should be placed by the APA2058' power pin to decouple the power rail noise. s
Copyright (c) ANPEC Electronics Corp. Rev. A.3 - Aug., 2008
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APA2058
Package Information
TQFN5x5-32A
D A
E
D2
A1 A3
Pin 1 Corner E2
e S Y M B O L A A1 A3 b D D2 E E2 e L K 0.35 0.20 0.18 4.90 3.10 4.90 3.10 0.50 BSC 0.45 0.014 0.008 TQFN5x5-32A MILLIMETERS MIN. 0.70 0.00 0.20 REF 0.30 5.10 3.50 5.10 3.50 0.007 0.193 0.122 0.193 0.122 0.020 BSC 0.018 MAX. 0.80 0.05 MIN. 0.028 0.000 0.008 REF 0.012 0.201 0.138 0.201 0.138 INCHES MAX. 0.031 0.002
Copyright (c) ANPEC Electronics Corp. Rev. A.3 - Aug., 2008
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LK
b
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APA2058
Carrier Tape & Reel Dimensions
OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B
d
Application
A
H
H A
T1
330.0O .00 50 MIN. 2 TQFN5x5-32A P0 4.0O .10 0 P1 8.0O .10 0
T1 C d D W E1 12.4+2.00 13.0+0.50 0 0 -0.00 -0.20 1.5 MIN. 20.2 MIN. 12.0O .30 1.75O .10 P2 2.0O .10 0 D0 1.5+0.10 -0.00 D1 1.5 MIN.
W
F 5.5O .10 0
T A0 B0 K0 0.6+0.00 0 0 0 -0.40 5.30O .20 5.30O .20 1.30O .20
(mm)
Devices Per Unit
Package Type TQFN5x5-32A Unit Tape & Reel Quantity 2500
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APA2058
Taping Direction Information
TQFN5x5-32A
USER DIRECTION OF FEED
Reflow Condition
TP
(IR/Convection or VPR Reflow)
tp Critical Zone TL to TP Ramp-up
TL
Temperature
tL Tsmax
Tsmin Ramp-down ts Preheat
25
t 25C to Peak
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78
27
Time
Description 245C, 5 sec 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA
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APA2058
Classification Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Time 25C to Peak Temperature Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds 6C/second max. 6 minutes max. Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds 6C/second max. 8 minutes max.
Note: All temperatures refer to topside of the package. Measured on the body surface.
Table 1. SnPb Eutectic Process - Package Peak Reflow Temperatures Package Thickness <2.5 mm 2.5 mm Volume mm <350 240 +0/-5C 225 +0/-5C
3
Volume mm3 350 225 +0/-5C 225 +0/-5C
Table 2. Pb-free Process - Package Classification Reflow Temperatures Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm - 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level. Package Thickness
3 3 3
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838
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